View AD9100JD_4191773.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

functional block diagram a1 v in clk clk a2 switch 50 v ad9100 6 2.3v clamp c hold 22pf v out rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ultrahigh speed monolithic track-and-hold ad9100* features excellent hold mode distortion into 250 v C88 db @ 30 msps (2.3 mhz v in ) C83 db @ 30 msps (12.1 mhz v in ) C74 db @ 30 msps (19.7 mhz v in ) 16 ns acquisition time to 0.01% <1 ps aperture jitter 250 mhz tracking bandwidth 83 db feedthrough rejection @ 20 mhz 3.3 nv/ ? hz spectral noise density mll-std-compliant versions available applications a/d conversion direct if sampling imaging/flir systems peak detectors radar/ew/ecm spectrum analysis ccd ate general description the ad9100 is a monolithic track-and-hold amplifier which sets a new standard for high speed and high dynamic range applications. it is fabricated in a mature high speed complemen- tary bipolar process. in addition to innovative design topologies, a custom package is utilized to minimize parasitics and optimize dynamic performance. acquisition time (hold to track) is 13 ns to 0.1% accuracy, and 16 ns to 0.01%. the ad9100 boasts superlative hold-mode frequency domain performance; when sampling at 30 msps hold mode distortion is less than 83 dbfs for analog frequencies up to 12 mhz; and C74 dbfs at 20 mhz. the ad9100 can also drive capacitive loads up to 100 pf with little degradation in acquisition time; it is therefore well suited to drive 8- and 10-bit flash converters at clock speeds to 50 msps. with a spectral noise density of 3.3 nv/ ? hz and feedthrough rejection of 83 db at 20 mhz, the ad9100 is well suited to enhance the dynamic range of many 8- to 16-bit systems. the ad9100 is user friendly and easy to apply: (1) it requires +5 v/C5.2 v power supplies; (2) the hold capacitor and switch power supply decoupling capacitors are built into the dip pack- age; (3) the encode clock is differential ecl to minimize clock jitter; (4) the input resistance is typically 800 k w ; (5) the analog input is internally clamped to prevent damage from voltage transients. the ad9100 is available in a 20-lead side-brazed skinny dip package. commercial, industrial, and military temperature grade parts are available. consult the factory for information about the availability of 883-qualified devices. product highlights 1. hold mode distortion is guaranteed. 2. monolithic construction. 3. analog input is internally clamped to protect against over- voltage transients and ensure fast recovery. 4. output is short circuit protected. 5. drives capacitive loads to 100 pf. 6. differential ecl clock inputs. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 * patent pending.
rev. b C2C ad9100Cspecifications electrical characteristics test AD9100JD/ad/sd 1 parameter conditions temp level min typ max units dc accuracy gain d v in = 2 v full vi 0.989 0.994 v/v offset v in = 0 v full vi C5 1+5mv output resistance 25 c v 0.4 w output drive capability full vi 40 60 ma psrr d v s = 0.5 v p-p full vi 48 55 db pedestal sensitivity to supply d v s = 0.5 v p-p full vi 0.9 3 mv/v analog input/output output voltage range full vi +2 2.2 C2 v input bias current 25 cviC8 3+8 m a full vi C16 +16 m a input overdrive current 2 v in = 4 v; r in = 50 w 25 cv 22 ma input capacitance 25 c v 1.2 pf input resistance 25 c, t max vi 350 800 k w t min vi 200 k w clock/ clock inputs input bias current cl/ cl = C1.0 v full vi 4 5 ma input low voltage (v il ) full vi C1.8 C1.5 v input high voltage (v ih ) full vi C1.0 C0.8 v track mode dynamics bandwidth (C3 db) v out 0.4 v p-p full iv 150 250 mhz slew rate 4 v step 25 c iv 550 850 v/ m s 4 v step full iv 500 v/ m s overdrive recovery time 2 (to 0.1%) v in = 4 v to 0 v 25 cv 21 ns 2nd harm. dist. (20 mhz, 2 v p-p) full v C65 dbc 3rd harm. dist. (20 mhz, 2 v p-p) full v C75 dbc integrated output noise (1-200 mhz) 25 cv 45 m v rms spectral noise @ 10 mhz 25 c v 3.3 nv/ ? hz hold mode dynamics worst harmonic (2.3 mhz, 30 msps) v out = 2 v p-p 25 c v C83 dbfs worst harmonic (12.1 mhz, 30 msps) v out = 2 v p-p 25 c iv C80 C72 dbfs worst harmonic (12.1 mhz, 30 msps) v out = 2 v p-p t max iv C70 dbfs worst harmonic (12.1 mhz, 30 msps) v out = 2 v p-p t min iv C77 C68 dbfs worst harmonic (19.7 mhz, 30 msps) v out = 2 v p-p 25 c v C74 dbfs hold noise 3 25 c v 300 3 t h v/s rms droop rate 4 v in = 0 v 25 cvi 110 mv/ m s t min vi 7 40 mv/ m s t max vi 5 30 mv/ m s feedthrough rejection (20 mhz) v in = 2 v p-p full v 83 db track-to-hold switching aperture delay 25 c v +800 ps aperture jitter 25 cv < 1ps pedestal offset v in = 0 v 25 cviC8 1+8mv full vi C10 +10 mv transient amplitude v in = 0 v full v 6mv settling time to 1 mv full iv 7 10 ns glitch product v in = 0 v 25 c v 15 pv-s hold-to-track switching acquisition time to 0.1% 2 v step 25 cv 13 ns acquisition time to 0.01% 2 v step full iv 16 23 ns acquisition time to 0.01% 4 v step 25 cv 20 ns power supply power dissipation full vi 1.05 1.25 w +v s current full vi 96 118 ma Cv s current full vi 116 132 ma notes 1 AD9100JD: 0 c to +70 c. ad9100ad: C40 c to +85 c. ad9100sd: C55 c to +125 c. dip q ja = 38 c/w; this is valid with the device mounted flush to a grounded 2 oz. copper clad board with 16 sq. inches of surface area and no air flow. 2 the input to the ad9100 is internally clamped at 2.3 v. the internal input series resistance is nominally 50 w . 3 hold mode noise is proportional to the length of time a signal is held. for example, if the hold time (t h ) is 20 ns, the accumulated noise is typically 6 m v (300 v/s 3 20 ns). this value must be combined with the track mode noise to obtain total noise. 4 min and max droop rates are based on the military temperature range (C55 c to +125 c). refer to the droop rate vs temperature chart for min/max limits over the commercial and industrial ranges. specifications subject to change without notice. (unless otherwise noted, +v s = +5 v; Cv s = C5.2 v; r load = 100 v ; r in = 50 v )
ad9100 rev. b C3C explanation of test levels test level i C 100% production tested. ii C 100% production tested at +25 c, and sample tested at specified temperatures. iii C periodically sample tested. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C all devices are 100% production tested at +25 c. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices. ordering guide temperature package package model* range description option AD9100JD 0 c to +70 c ceramic dip d-20 ad9100ad C40 c to +85 c ceramic dip d-20 ad9100sd C55 c to +125 c ceramic dip d-20 *consult factory about availability of parts screened to mil-std-883. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9100 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device evaluation board ordering information part number description ad9100/pwb printed wiring board (only) of evaluation circuit ad9100/pcb evaluation board for ad9100t/h, assembled and tested [order ad9100t/h (dip) separately] clock inputs +2v 0v C2v analog input +2v 0v C2v "1" "0" clock (pin #19) clock hold to track switch delay time (4ns) aperture delay (0.8ns) "track" voltage level held "hold" "hold" track to hold settling (7ns) hold capacitor/ analog output observed at hold capacitor observed at analog output acquisition time (16ns) figure 1. timing diagram (1 ns/div) absolute maximum ratings 1 supply voltages ( v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v continuous output current . . . . . . . . . . . . . . . . . . . . . 70 ma analog input voltage 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 v operating temperature range (case) AD9100JD . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c ad9100ad . . . . . . . . . . . . . . . . . . . . . . . . . C25 c to +85 c ad9100sd . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175 c storage temperature . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead soldering temperature (10 sec) . . . . . . . . . . . . . +300 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 analog input voltage should not exceed v s .
ad9100 rev. b C4C pin function descriptions/connections pin no. description connection 1Cv s C5.2 v power supply 2, 3, 8, 10C13, 17 gnd common ground plane 4v in analog input signal 5, 7 Cv s C5.2 v power supply 6, 15 bypass 0.1 m f to ground 9v out track-and-hold output 14, 16, 20 +v s +5 v, power supply 18 clk complement ecl clock 19 clk true ecl clock chip pad assignments gnd nc clock nc hold cap (note 3) 2 3 4 5 6 7 8 9 10 11 12 32 14 15 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 +v s cap (note 1) clock gnd nc bypass (note 2) ad9100 top view (not to scale) +v s +v s +v s +v s +v s +v s bypass (note 2) +v s +v out Cv s Cv in Cv s Cv s cap (note 1) Cv s size = 148 3 63 3 15 mils nc = no connect notes: 1. supply bypass capacitor; 0.01 to 0.1 m f ceramic connected to ground. 2. 0.01 m f ceramic connected between pad 29 and pad 31. 3. hold capacitor connected from pad 4 and pad 5 to ground; 10C100pf, nominally 22pf. dip package does not require external hold capacitor. 1 13 27 bypass Cv s gnd +v s clk Cv s Cv s +v s bypass +v s gnd v in clk gnd gnd gnd v out gnd gnd gnd top view (not to scale) ad9100 pin configuration 20-lead side-brazed ceramic dip terminology analog delay is the time required for an analog input signal to propagate from the device input to output. aperture delay tells when the input signal is actually sampled. it is the time difference between the analog propagation delay of the front-end buffer and the control switch delay time. (the time from the hold command transition to when the switch is opened.) for the ad9100, this is a positive value which means that the switch delay is longer than the analog delay. aperture jitter is the random variation in the aperture delay. this is measured in ps-rms and results in phase noise on the held signal. droop rate is the change in output voltage as a function of time (dv/dt). it is measured at the ad9100 output with the device in hold mode and the input held at a specified dc value, the measurement starts immediately after the t/h switches from track to hold. feedthrough rejection is the ratio of the input signal to the output signal when in hold mode. this is a mea- sure of how well the switch isolates the input signal from feeding through to the output. hold-to-track switch delay is the time delay from the track command to the point when the output starts to change and acquire a new signal. pedestal offset is the offset voltage step measured immediately after the ad9100 is switched from track to hold with the input held at zero volts. it manifests itself as an added offset during the hold time. track-to-hold settling time is the time necessary for the track to hold switching transient to settle to within 1 mv of its final value. track-to-hold switching transient is the maximum peak switch induced transient voltage which appears at the ad9100 output when it is switched from track to hold.
50 0 100 30 10 20 20 0 40 80 60 40 c C pf load r s C v no r s needed when c l is less than 6pf r s c l 1k v ad9100 figure 4. recommended r s vs. c load for optimal settling times 100ns/div 2mv/div 10ns track hold track clk clk 10ns figure 7. track-to-hold-to-track switch transients 58 50 dc 20 56 52 5 54 15 10 input frequency C mhz snr, including harmonics C db ad9060 + ad9100 c hold = 10pf c hold = 22pf a in = 3.5v p-p encode = 20 msps ad9060 figure 10. snr vs. analog input 60 10 300 40 20 60 30 dc 50 240 180 120 input frequency C mhz psrr C db figure 3. power supply rejection ratio vs. frequency 50 0 +125 30 10 +25 20 C50 40 +75 0 typical worst case mv/ m s temperature C 8 c figure 6. magnitude of droop rate vs. temperature 27 v ad9100 10 a in c h * the ad9060 is a 10-bit, 75msps monolithic adc from analog devices. * the ad9100xd (dip) has an internal 22pf hold capacitor. ad9060 fft proc figure 9. 1.0 10 20 0.1 0.01 12 16 18 14 ns % of full scale v out = 2v step 0.001 figure 12. settling tolerance vs. acquisition time 0 C10 C5 300 60 dc 240 180 120 input frequency C mhz gain C db figure 2. gain vs. frequency (track mode) C95 C70 20 C85 C75 4 C80 0 C90 16 12 8 input frequency C mhz dbc v o = 2v p-p encode = 30 msps r l = 250 v r l = 100 v figure 5. worst hold mode harmonic vs. analog input frequency 58 43 dc 40 53 48 10 20 30 input frequency C mhz snr, including harmonics C db c hold = 22pf ad9060 a in = 3.5v p-p encode = 40 msps ad9060 + ad9100 c hold = 10pf figure 8. snr vs. analog input 100 2 120 10 input frequency C mhz 105 55 85 65 75 95 db beyond capability of available measurement tools figure 11. feedthrough rejection vs. input frequency typical performance characteristicsCad9100 rev. b C5C
ad9100 rev. b C6C acquisition time acquisition time is the amount of time it takes the ad9100 to reacquire the analog input when switching from hold to track mode. the interval starts at the 50% clock transition point and ends when the input signal is reacquired to within a specified error band at the hold capacitor. the hold to track switch delay (t dh t) cannot be subtracted from this acquisition time because it is a charging time delay that occurs when moving from hold to track; this is typically 4 ns to 6 ns and is the longest delay. therefore, the track time required for the ad9100 is the acquisition time minus the aper- ture delay time. note that the acquisition time is defined as the settled voltage at the hold capacitor and does not include the delay and settling time of the output buffer. the example below illustrates why the output buffer amplifier does not contribute to the overall ad9100 acquisition time. c h v ch input buffer v out v in track hold time peak transient seen by output buffer t dht 6ns v ch v out acquisition time at c h to x% output buffer t s figure 13. acquisition time diagram the exaggerated illustration in figure 13 shows that v ch has settled to within x% of its final value, but v out (due to slew rate limitations, finite bw, power supply ringing, etc.) has not settled during the track time. however, since the output buffer always tracks the front end circuitry, it catches up during the hold time and directly superimposes itself (less about 600 ps of analog delay) to v ch . since the small-signal settling time of the output buffer is about 1.8 ns to 1 mv and is significantly less than the specified hold time, acquisition time should be referenced to the hold capacitor. note that most of the hold settling time and output acquisition time are due to the input buffer and the switch network. for track time, the output buffer contributes only about 5 ns of the total; in hold mode, it contributes only 1.8 ns (as stated above). a stricter definition of acquisition time would total the acquisi- tion and hold times to a defined accuracy. to obtain 12 bit + distortion levels and 30 msps operation, the recommended track and hold times are 20 ns and 13.5 ns, respectively. to drive an 8-bit flash converter with a 2 v p-p full-scale input, hold time to 1 lsb accuracy will be limited primarily by the encoder, rather than by the ad9100. this makes it possible to reduce track time to approximately 13 ns, with hold time chosen to optimize the encoders performance. theory of operation the ad9100 utilizes a new track and hold architecture. previ- ous commercially available high speed track and holds used an open loop input buffer, followed by a diode bridge, hold capaci- tor, and output buffer (closed or open loop) with a fet device connected to the hold capacitor. this architecture required mixed device technology and, usually, hybrid construction. the sampling rate of these hybrids has been limited to 20 msps for 12-bit accuracy. distortion generated in the front-end amplifier/ bridge limited the dynamic range performance to the mid-70 dbfs for analog input signals of less than 10 mhz. broadband and switch-generated noise limited the snr of previous track and holds to about 70 db. the ad9100 is a monolithic device using a high frequency complementary bipolar process to achieve new levels of high speed precision. its patent pending architecture breaks from the traditional architecture described above. (see the block diagram on the first page.) the switching type bridge has been integrated into the first stage closed loop input amplifier. this innovation provides error (distortion) correction for both the switch and amplifier, while still achieving slew rates representative of an open-loop design. in addition, acquisition slew current for the hold capacitor is higher than standard diode bridge and switch configurations, removing a main contributor to the limits of maximum sampling rate and input frequency. switching circuits in the device use current steering (versus voltage switching) to provide improved isolation between the switch and analog sections. this results in low aperture time sensitivity to the analog input signal, and reduced power supply and analog switching noise. track to hold peak switching tran- sient is typically only 6 mv and settles to less than 1 mv in 7 ns. in addition, pedestal sensitivity to analog input voltage is very low (0.6 mv/v) and being first order linear does not significantly affect distortion. the closed-loop output buffer includes zero voltage bias current cancellation, which results in high-temperature droop rates equivalent to those found in fet type inputs. the buffer also provides first order quasistatic bias correction resulting in an extremely high input resistance and very low droop sensitivity vs. input voltage level (typically less than 1.5 mv/vC m s.) this closed-loop architecture inherently provides high speed loop correction and results in low distortion under heavy loads. the extremely fast time constant linearity (7 ns to 0.01% for a 2 v step) ensures that the output buffer does not limit the ad9100 sampling rate or analog input frequency. (the acquisi- tion and settling time are primarily limited only by the input amplifier and switch.) the output is transparent to the overall ad9100 hold mode distortion levels for loads as low as 250 w . full-scale track and acquisition slew rates achieved by the ad9100 are 800 and 1000 v/ m s, respectively. when combined with excellent phase margin (typically 5% overshoot), wide bandwidth, and dc gain accuracy, acquisition time to 0.01% is only 16 ns. though not production tested, settling to 14-bit accuracy (C86 db distortion @ 2.3 mhz) can be inferred to be 20 ns.
ad9100 rev. b C7C hold vs. track mode distortion in many traditional high speed, open loop track-and-holds, track mode distortion is often much better than hold mode distortion. track mode distortion does not include nonlineari- ties due to the switch network, and does not correlate to the relevant hold mode distortion. but since hold mode distortion has traditionally been omitted from manufacturers specification tables, users have had to discover for themselves the effective overall hold mode distortion of the combined t/h and encoder. the architecture of the ad9100 minimizes hold mode distortion over its specified frequency range. as an example, in track mode the worst harmonic generated for a 20 mhz input tone is typi- cally C65 dbfs. in hold mode, under the same conditions and sampling at 30 msps, the worst harmonic generated is C74 dbfs. the reason is the output buffer in hold mode has only dc distortion relevancy. with its inherent linearity (7 ns settling to 0.01%), the output buffer has essentially settled to its dc distortion level even for track plus hold times as short as 30 ns. for a traditional open-loop output buffer, the ac (track mode) and dc (hold mode) distortion levels are often the same. droop rate droop rate does not necessarily affect a track and holds distor- tion characteristics. if the droop rate is constant versus the input voltage for a given hold time, it manifests itself as a dc offset to the encoder. for the ad9100, the droop rate is typically 1 mv/ m s. if a signal is held for 1 m s, a subsequent encoder would see a 1 mv offset voltage. if there is no droop sensitivity to the held voltage value, the 1 mv offset would be constant and ride on the input signal and introduce no hold-mode nonlinearities . in instances in which droop rate varies proportionately to the magnitude of the held voltage signal level, a gain error only is introduced to the a/d encoder. the ad9100 has a droop sensi- tivity to the input level of 1.5 mv/ vC m s. for a 2 v p-p input signal, this translates to a 0.15%/ m s gain error and does not cause additional distortion errors. for the ad9100, droop sensitivity to input level is insignificant. however, hold times longer than about 2 m s can cause distortion due to the r 3 c h time constant at the hold capacitor. in addition, hold mode noise will increase linearly vs. hold time and thus degrade snr performance. layout considerations for best performance results, good high speed design tech- niques must be applied. the component (top) side ground plane should be as large as possible; two-ounce copper cladding is preferable. all runs should be as short as possible, and decou- pling capacitors must be used. figure 14 is the schematic of a recommended ad9100 evalua- tion board. (contact factory concerning availability of assembled boards.) all 0.01 m f decoupling capacitors should be low induc- tance surface mount devices (p/n 05085c103mt050 from avx) and connected on the component side within 30 mils of the designated pins; with the other sides soldered directly to the top ground plane. dut (dip) ad9100 c3 c1 c7 c6 c8 c5 ad9620 ad96685 c13 10 m f tp3 +v s j7 j6 j5 Cv s c14 10 m f tp1 j1 v in c2 c4 j2 v out j3 v buff r l 2k v +v s Cv s c10 q q le r2 6 v w1 w2 r1 100 v clock in +5v C5.2v r4 510 v r5 510 v r in 50 v note: connect to w1 for ttl clock signals; connect to w2 for ground-referenced signals. r s 5 v c9 + r3 4 v figure 14. ad9100/pcb evaluation board diagram the 10 m f low frequency power supply tantalum decoupling capacitors should be located within 1.5 inches of the ad9100. the common 0.01 m f supply capacitors can be wired together. the common power supply bus (connected to the 10 m f capaci- tor and power supply source) can be routed to the underside of the board to the daisy chain wired 0.01 m f supply capacitors. for remote input and/or output drive applications, controlled impedances are required to minimize line reflections which will reduce signal fidelity. when capacitive and/or high impedance levels are present, the load and/or source should be physically located within approximately one inch of the ad9100. note that a series resistance, r s , is required if the load is greater than 6 pf. (the recommended r s vs. cl chart in the typical performance section shows values of r s for various capacitive loads which result in no more than a 20% increase in settling time for loads up to 80 pf.) as much of the ground plane as possible should be removed from around the v in and v out pins to minimize coupling onto the analog signal path. while a single ground plane is recommended, the analog signal and differential ecl clock ground currents follow a narrow path directly under their common voltage signal line. to reduce reflections, especially when terminations are used for transmission line efficiency, the clock, v in , and v out signals and respective ground paths should not cross each other; if they do, unwanted coupling can result. high current ground transients via the high frequency decou- pling capacitors can also cause unwanted coupling to the v in and v out current loops. therefore, these analog terminations should be kept as far as possible from the power supply decou- pling capacitors to minimize feedthrough.
ad9100 rev. b C8C using sockets pin sockets (p/n 6-330808-3 from amp) should be used if the device can not be soldered directly to the pcb. high profile or wire wrap type sockets will dramatically reduce the dynamic performance of the device in addition to increasing the case-to- ambient thermal resistance. driving the encode clock the ad9100 requires a differential ecl clock command. due to the high gain bandwidth of the ad9100 internal switch, the input clock should have a slew rate of at least 100 v/ m s. to obtain maximum signal to noise performance, especially at high analog input frequencies, a low jitter clock source is re- quired. the ad9100 clock can be driven by an ad96685, an ultrahigh speed ecl comparator with very low jitter. 150 v 150 v 1k v 1k v clk clk C5.2v C5.2v figure 15. clock/ clock input stage driving the analog input special care must be taken to ensure that the analog input signal is not compromised before it reaches the ad9100. to obtain maximum signal to noise performance, a very low phase noise analog source is required. in addition, input filtering and/or a low harmonic signal source is necessary to maximize the spuri- ous free dynamic range. any required filtering should be done close to the ad9100 and away from any digital lines. overdriving the analog input the ad9100 has input clamps that prevent hard saturation of the output buffer, thereby providing fast overvoltage recovery when the analog input transitions to the linear region ( 2 v). the clamps are set internally at 2.3 v and cannot be altered by the user. the output settles to 0.1% of its value 21 ns after the overvoltage condition is alleviated. when the analog input is outside the linear region, the analog output will be at either +2.2 v or C2.2 v. matching the ad9100 to a/d encoders the ad9100s analog output level may have to be offset or amplified to match the full-scale range of a given a/d converter. this can generally be accomplished by inserting an amplifier after the ad9100. for example, the ad671 is a 12-bit 500 ns monolithic adc encoder that requires a 0 to +5 v full-scale analog input. an ad84x series amplifier could be used to con- dition the ad9100 output to match the full-scale range of the ad671. ultralow distortion/low resistive load applications when driving low resistive loads or when the widest possible spurious free dynamic range is required, system performance can be improved by isolating the load from the ad9100. (see figure 16.) the ad9620 low distortion closed-loop buffer amplifier has an input resistance of 800 k w and generates har- monics that are less than those generated by the ad9100. other buffers should not be considered if their harmonics are not lower than those of the ad9100. ad9620 analog input into low resistive load ad9100 figure 16. using ad9620 as isolation amplifier direct if conversion the ad9100 can be used to sample super-nyquist signals, making wide dynamic range direct if to digital conversion prac- tical. by reducing the analog input level to the track and hold, distortion due to the ad9100 can be minimized. as the input level is reduced, the gain in the output amplifier (see figure 17) must be increased to match the full scale level of the subsequent analog-to-digital converter. ad9100 post-amp adc ad9618 t/h clock adc clock if input 6 100 mv hold track "1" "0" t/h clock adc clock 20ns 5ns gain adj to utilize max adc range figure 17. if sampling with track-and-hold this technique is not confined to processing nyquist signals. figure 18 illustrates the spurious free dynamic range of the ad9100 as a function of analog input signal level and fre quency. without the output amplifier (2 v p-p input), 70 db+ dynamic range is observed only to about 24 mhz. by reducing the analog input to 200 mv p-p, >70 db sfdr can be maintained to 70 mhz ifs. the optimum t/h input level for a particular if can be deter- mined by examining the t/h spurious and noise performance. the highest input signal level which will provide the required sfdr gives the lowest noise performance. when sampling super nyquist signals, the if will be aliased to baseband and can be observed by using fft analysis. 70 80 60 10 70 50 60 40 30 20 0 50 90 input frequency C mhz spurious-free dynamic range C dbc 200mv p-p input 500mv p-p input 2v p-p input figure 18. sfdr vs. input frequency at 10 msps
ad9100 rev. b C9C in the fft spectrum below (see figure 19), the 71.4 mhz if is observed at 1.4 mhz. note that the highest frequency observed (fs/2) is determined by the sample rate of the t/h. 0 C100 5.0 C80 dc C40 C60 C20 4.0 3.0 2.0 1.0 frequency C mhz 78 68 2 5 3 4 figure 19. 71.4 mhz signal sampled at 10 msps with 200 mv p-p input low noise applications when processing low level single event signals in which noise performance is the primary concern, amplification ahead of the ad9100 can increase overall system signal to noise ratio. front- end amplification often results in an increase in hold mode distortion levels because of the track mode limitations of the amplifier which is used. depending on the signal levels and bandwidth, the ad9618 low noise high gain amplifier is a pos- sible candidate for this application. see figure 20. as a general rule, if the goal is maximize snr (minimize noise), pre-ad9100 amplification is recommended. when the system goal is to maximize the spurious free dynamic range (minimize distortion), post-ad9100 amplification is recommended. ad9618 low level source to encoder ad9100 figure 20. using ad9618 as pre-amp for ad9100
ad9100 rev. b C10C time C ns 0.025% 0.1% 0.025% 0.1% 10 040 30 20 c hold voltage track command (not to scale) 2v input step 100 v load measurement point input buffer v in c hold +1v C1v reference figure 21. acquisition time time C ns 0.025% 0.1% 0.025% 0.1% 10 040 30 20 track command (not to scale) 2v input step 100 v load reference output buffer +1v C1v v out r hold measurement point c hold v out figure 22. output acquisition time 9 7 6 58 4 3 2 0 120 60 100 80 20 40 db below full scale v out = 2v p-p r load = 250 v encode = 30 msps t track = 20ns t track = 13.5ns figure 23. frequency (500 khz/division) analog input = 540 khz 958 47 6 3 2 0 120 60 100 80 20 40 db below full scale v out = 2v p-p r load = 250 v encode = 30 msps t track = 20ns t hold = 13.5ns all harmonics are aliased figure 24. frequency (500 khz/division) analog input = 2.3 mhz
ad9100 rev. b C11C 34809 (a) a 0.25 (6.35) 0.25 (6.35) 4 places 3.4 (86.36) 2.5 (63.5) figure 26. bottom of ad9100/pcb evaluation board viewed from above rs rin r3 r5 r4 r2 r1 u1 u2 dut ad9100 evaluation board tp3 tp1 w1 w3 w2 j4 clock in j2 vout j1 vin j3 vbuff rl c12 c13 +vs gnd Cvs j7 j6 j5 figure 28. top of ad9100/pcb evaluation board viewed from above 9 7 6 2 8 5 4 3 0 120 60 100 80 20 40 db below full scale v out = 2v p-p r load = 100 v encode = 30 msps t track = 20ns t hold = 13.5ns all harmonics are aliased figure 25. frequency (500 khz/division) analog input = 12.1 mhz 0 120 60 100 80 20 40 db below full scale v out = 2v p-p r load = 100 v encode = 30 msps t track = 20ns t hold = 13.5ns all harmonics are aliased figure 27. frequency (500 khz/division) analog input = 19.8 mhz
ad9100 rev. b C12C outline dimensions dimensions shown in inches and (mm). c1513aC0C6/98 printed in u.s.a. 20-lead side-brazed ceramic dip (d-20) 20 1 10 11 pin 1 identifier 0.100 (2.54) typ seating plane 0.150 (3.81) min 0.290 6 0.010 (7.366 6 0.254) 0.05 (1.27) typ 0.020 (0.51) 0.016 (0.41) 0.020 6 0.005 (0.508 6 0.127) 1.052 6 0.011 (26.721 6 0.279) 0.175 (4.45) max 0.010 6 0.002 (0.254 6 0.051) 0.300 (7.62) ref

▲Up To Search▲

Price & Availability of AD9100JD

	To Download AD9100JD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .